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MICRF500
The bit setting that corresponds to lock can vary, depending
on temperature, loop filter and type of varactor. Therefore, the
lock detect circuit needs to be calibrated regularly by a
software routine that finds the correct bit setting, by running
through all combinations of bits Ref0 – Ref5. Depending on
the size of the reference window, there will be several bit
combinations that show lock. For instance, with a large
reference window, as much as five bit combinations can
make the lock detector show lock. To have the maximum
robustness to noise, the third of the bit settings should be
chosen.
Charge Pump
The charge pump can be programmed to four different modes
with two currents, ± 125 μ A and ± 500 μ A. Bit 70 and 71 in the
control word (cpmp1 and cpmp0) controls the operation. The
four modes are:
1. cpmp1 = 0 Current is constant ± 125 μ A. Used in
cpmp0 = 0 applications where short PLL lock
time is not important.
2. cpmp1 = 0 Current is constant ± 500 μ A. Used in
cpmp0 = 1 applications where a short PLL lock
time is important, e.g., internal modula-
tion. See “ Modulation Inside PLL ”
section.
3. cpmp1 = 1 Current is ± 500 μ A when PLL is out of
cpmp0 = 0 lock and ± 125 μ A when it is in lock.
Controlled by LOCKDET (Pin 15). Lock
time is halved.
See “ Modulation Outside PLL ” section.
4. cpmp1 = 1 Same as above in Tx. In Rx the current
cpmp0 = 1 is ± 500 μ A. Used when using dual-loop
filters. See “ Modulation Outside PLL
Dual-Loop Filters ” section.
Tuning of VCO and XCO
There are two circuit blocks that may need tuning, the VCO
and the crystal oscillator.
VCO Tuning
When the VCO voltage is not at its mid-point, a capacitor may
be added in parallel with D1or by small increments changes
in the L1 or C13 values.
This is particularly important when using VCO modulation.
The gain curve of the VCO (MHz/Volt) is not linear and the
gain will therefore vary with loop voltage. This means that the
FSK frequency deviation also varies with loop voltage.
When using internal modulation, tuning the VCO can be
omitted as long as the VCO gain is large enough to allow the
PLL to handle variations in process parameters and tempera-
ture without going out of lock.
Micrel
FSK Modulation
The circuit has two sets of frequency dividers A0, N0, M0 and
A1, N1, M1. The frequency dividers are programmed via the
control word. A0, N0, M0 are to be programmed with the
receive frequency and are used in receive mode. There are
three ways of implementing FSK:
? FSK modulation can be applied to the VCO. This
way of implementing FSK modulation is ex-
plained more in detail in the next section. The
values corresponding to the transmit frequency
should be programmed in dividers A1, N1 and
M1. Pin DATAIXO must be kept in tri-state from
the time Tx-mode is entered until one starts
sending data.
? FSK modulation by switching between the two
sets of A, N and M dividers. A, N and M values
corresponding to the receive frequency and both
transmit frequencies have to be found. In
transmit the values corresponding to data ‘ 0 ’
should be programmed in dividers A0, N0 and
M0, and the values corresponding to data ‘ 1 ’
should be programmed in dividers A1, N1 and
M1.
? FSK modulation by adding/subtracting 1 to
divider A1. The frequency deviation will be equal
to the comparison frequency. The values
corresponding to the transmit frequency should
be programmed in dividers A1, N1 and M1.
For all types of FSK modulation, data is entered at the
DATAIXO pin.
Loop Filter
The design of the loop filter is of great importance for
optimizing parameters like modulation rate, PLL lock time,
bandwidth and phase noise. Low bitrates will allow modula-
tion inside the PLL, which means the loop will lock on different
frequency for 1s and 0s. This can be implemented by switch-
ing the internal dividers (M, N and A).
Higher modulation rates (above 2400bps) imply implementa-
tion of modulation outside the PLL. This can be implemented
by applying the modulation directly to the VCO.
Loop filter values can be found using an appropriate software
program.
Modulation Inside PLL
A fast PLL requires a loop filter with relatively high bandwidth.
If a second order loop filter is chosen, it may not give
adequate attenuation of the comparison frequency. There-
fore in the following example a third order loop filter is chosen.
Example 1:
XCO Tuning
Tune the trimming capacitor in the crystal oscillator to the
Radio frequency f RF
Comparison frequency f C
868MHz
100kHz
VCO gain K o
precise desired transmit frequency. It is not possible to tune
the crystal oscillator over a large frequency range. N, M and
A values must therefore be chosen to give a RF frequency
very close to the desired frequency. Because of the small
tuning range the VCO will not go out of lock when tuning the
crystal oscillator.
Loop bandwidth BW 3.8kHz
30MHz/V
Phase comparator gain K d 500 μ A/rad
Phase margin j 62 °
Breakthrough suppression A 20dB
MICRF500
10
March 2003
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